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<title>VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector </title></head>
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<h1>VGETMANTPS—Extract Float32 Vector of Normalized Mantissas from Float32 Vector</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.66.0F3A.W0 26 /r ib</p>
<p>VGETMANTPS xmm1 {k1}{z}, xmm2/m128/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Get normalized mantissa from float32 vector xmm2/m128/m32bcst and store the result in xmm1, using imm8 for sign control and mantissa interval normalization, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.256.66.0F3A.W0 26 /r ib</p>
<p>VGETMANTPS ymm1 {k1}{z}, ymm2/m256/m32bcst, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Get normalized mantissa from float32 vector ymm2/m256/m32bcst and store the result in ymm1, using imm8 for sign control and mantissa interval normalization, under writemask.</td></tr>
<tr>
<td>
<p>EVEX.512.66.0F3A.W0 26 /r ib</p>
<p>VGETMANTPS zmm1 {k1}{z}, zmm2/m512/m32bcst{sae}, imm8</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Get normalized mantissa from float32 vector zmm2/m512/m32bcst and store the result in zmm1, using imm8 for sign control and mantissa interval normalization, under writemask.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>FVI</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>Imm8</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Convert single-precision floating values in the source operand (the second operand) to SP FP values with the mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.</p>
<p>The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-bit memory location.</p>
<p>For each input SP FP value x, The conversion operation is:</p>
<p><em>GetMant</em>(<em>x</em>) = <em>±</em>2<em><sup>k</sup>|x.significand|</em></p>
<p>where:</p>
<p>1 <em>&lt;</em>= <em>|x.significand| &lt; </em>2</p>
<p>Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is even or odd. The sign of the final result is determined by sc and the source sign.</p>
<p>if interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in Figure 5-15.</p>
<p>Each converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a mantissa normalized to the range specified by interv.</p>
<p>The GetMant() function follows Table 5-9 when dealing with floating-point special numbers.</p>
<p>This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1 are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their previous values.</p>
<p>Note: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.</p>
<p><strong>Operation</strong></p>
<p>GetNormalizeMantissaSP(SRC[31:0] , SignCtrl[1:0], Interv[1:0])</p>
<p>{</p>
<p>// Extracting the SRC sign, exponent and mantissa fields</p>
<p>Dst.sign (cid:197) SignCtrl[0] ? 0 : Src[31];</p>
<p>// Get sign bit</p>
<p>Dst.exp (cid:197) SRC[30:23];</p>
<p>; Get original exponent value</p>
<p>Dst.fraction (cid:197) SRC[22:0];; Get original fraction value</p>
<p>ZeroOperand (cid:197) (Dst.exp = 0) AND (Dst.fraction = 0);</p>
<p>DenormOperand (cid:197) (Dst.exp = 0h) AND (Dst.fraction != 0);</p>
<p>InfiniteOperand (cid:197) (Dst.exp = 0FFh) AND (Dst.fraction = 0);</p>
<p>NaNOperand (cid:197) (Dst.exp = 0FFh) AND (Dst.fraction != 0);</p>
<p>// Check for NAN operand</p>
<p>IF (NaNOperand)</p>
<p>{</p>
<p>IF (SRC = SNaN) {Set #IE;}</p>
<p>Return QNAN(SRC);</p>
<p>}</p>
<p>// Check for Zero and Infinite operands</p>
<p>IF ((ZeroOperand) OR (InfiniteOperand)</p>
<p>{</p>
<p>Dst.exp (cid:197) 07Fh;</p>
<p>// Override exponent with BIAS</p>
<p>Return ((Dst.sign&lt;&lt;31) | (Dst.exp&lt;&lt;23) | (Dst.fraction));</p>
<p>}</p>
<p>// Check for negative operand (including -0.0)</p>
<p>IF ((Src[31] = 1) AND SignCtrl[1])</p>
<p>{</p>
<p>Set #IE;</p>
<p>Return QNaN_Indefinite;</p>
<p>}</p>
<p>// Checking for denormal operands</p>
<p>IF (DenormOperand)</p>
<p>{</p>
<p>IF (MXCSR.DAZ=1) Dst.fraction (cid:197) 0;// Zero out fraction</p>
<p>ELSE</p>
<p>{</p>
<p>// Jbit is the hidden integral bit. Zero in case of denormal operand.</p>
<p>Src.Jbit (cid:197) 0;</p>
<p>// Zero Src Jbit</p>
<p>Dst.exp (cid:197) 07Fh;</p>
<p>// Override exponent with BIAS</p>
<p>WHILE (Src.Jbit = 0) {</p>
<p>// normalize mantissa</p>
<p>Src.Jbit (cid:197) Dst.fraction[22];</p>
<p>// Get the fraction MSB</p>
<p>Dst.fraction (cid:197) (Dst.fraction &lt;&lt; 1);</p>
<p>// Start normalizing the mantissa</p>
<p>Dst.exp-- ;</p>
<p>// Adjust the exponent</p>
<p>}</p>
<p>SET #DE;</p>
<p>// Set DE bit</p>
<p>}</p>
<p>}</p>
<p>// At this point, Dst.fraction is normalized.</p>
<p>// Checking for exponent response</p>
<p>Unbiased.exp (cid:197) Dst.exp – 07Fh;</p>
<p>// subtract the bias from exponent</p>
<p>IsOddExp (cid:197) Unbiased.exp[0];</p>
<p>// recognized unbiased ODD exponent</p>
<p>SignalingBit (cid:197) Dst.fraction[22];</p>
<p>CASE (<em>interv</em>[1:0])</p>
<p>00: Dst.exp (cid:197) 07Fh;</p>
<p>// This is the bias</p>
<p>01: Dst.exp (cid:197) (IsOddExp) ? 07Eh : 07Fh;</p>
<p>// either bias-1, or bias</p>
<p>10: Dst.exp (cid:197) 07Eh;</p>
<p>// bias-1</p>
<p>11: Dst.exp (cid:197) (SignalingBit) ? 07Eh : 07Fh;</p>
<p>// either bias-1, or bias</p>
<p>ESCA</p>
<p>// Form the final destination</p>
<p>DEST[31:0] (cid:197) (Dst.sign &lt;&lt; 31) OR (Dst.exp &lt;&lt; 23) OR (Dst.fraction);</p>
<p>Return (DEST);</p>
<p>}</p>
<p>SignCtrl[1:0] (cid:197) IMM8[3:2];</p>
<p>Interv[1:0] (cid:197) IMM8[1:0];</p>
<p><strong>VGETMANTPS (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN</p>
<p>IF (EVEX.b = 1) AND (SRC *is memory*)</p>
<p>THEN</p>
<p>DEST[i+31:i] (cid:197)(cid:3)GetNormalizedMantissaSP(SRC[31:0], sc, interv)</p>
<p>ELSE</p>
<p>DEST[i+31:i] (cid:197)(cid:3)GetNormalizedMantissaSP(SRC[i+31:i], sc, interv)</p>
<p>FI;</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);</p>
<p>VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn;</p>
<p>VGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn);</p>
<p>VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);</p>
<p>VGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r);</p>
<p>VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r);</p>
<p>VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);</p>
<p>VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn);</p>
<p>VGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn);</p>
<p>VGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn);</p>
<p>VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);</p>
<p>VGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Denormal, Invalid</p>
<p><strong>Other Exceptions</strong></p>
<p>See Exceptions Type E2.</p>
<table>
<tr>
<td>#UD</td>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>